Honored Contributor
Honored Contributorwhy is that O.K? you do not have even slightest pity to me :) .why can't altera be filled? my boss has a project that fills 115 000lcell cyclone IV. he has 24 separate high speed streams of wide buses that smashes into the fpga simultaneously; and all of them have their own separate processing tracts, each takes tens and tens of modules. and all of them are interconnected.pipeline registers only, exceed 5000. plus our devices have multiple motherboards positioned on top of each other (with separation of course) with single central processor fpga on each and lots of other IC s in surrounding areas.so quite a logic is dedicated to inter-IC and inter-motherboard communication. control section, and automatic recovery system(in case if remote update or something else goes wrong). he uses an fpga as if it was a set of multiple ICs under a single package. and MAX10 is a tiny puppy that can be filled easily. you see, some companies can not plan ahead how much logic will be enough. many companies take on building version 2.0 right after 1.0 touches the market. and that 2.0 drags all the circuits that were already implemented in the previous version. years of work add up, module after module, creating a huuuge monster that compiles for many hours. and in the end, ...there is no end. then it will be 3.0, 4.0 and so on. in such environment no logic resource is ever enough. and companies do not want to retrace their motherboards and hook onto higher capacity fpgas, it is too time consuming and expensive for them. that is why they are forced to try and stick as much logic as possible into the already soldered fpgas; and adding Doughterboards,additional motherboards and similar crapness. there in no such thing as well planned project in their work.
