Contributor
Regular ContributorHi,
There is some example designs available on Intel website like this one:
I2C Remote System Update Example | Design Store for Intel® FPGAs
This one includes an I2C interface with NIOS processor. You may replace with UART IP, if you will.
You can also look into Remote Update Intel FPGA IP User Guide. Though it does not support MAX 10, but you can take some reference from there.
Regards.
ContributorThanks, I saw that design example before. But in this example requires 2 FPGA for communicating with i2c because Quartus don't allow to flash the code in the irrelevent device. I have 1 FPGA and it is 10M08. There is very common example such as AN741 but in that example they use Nios II and they boot it from qspi they said it is because of they cannot boot Nios II from the on-chip memory because the on-chip already used by FPGA to store RSU files. But my mind confused here because RSU stored in CFM sectors but Nios II boot from UFM sectors of on-chip memory. How can they get mixed? There is plenty options to boot Nios II but I don't know exactly which one works in my FPGA but I'll try it anyway.
