Forum Discussion

New Contributor

5 years ago

MAX10 Damaged with clk pin pulled down

Hello, On my new design, I observe recurring FPGA MAX10 failures. The board has 6 similarly polarized FPGAs 10M08SCU169I7G . The FPGAs are programmed correctly, run fine for a few hours and then on...

JonWay_altera

Frequent Contributor

5 years ago

You might want to

1) Check if there is any chance you have violated the absolute max spec: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf (Table 4)

2) Check if it could be due to ESD.

Forum Discussion

MAX10 Damaged with clk pin pulled down

Recent Discussions

IBIS models GTS banks agilex 5E

Clarification on Arria 10 Design Security Features

rsu_client failing to write to slot

Netlength Agilex5 028B

Agilex 7 Decoupling capacitor scaling factor