MAX10 constraining IO problems

Ok, I found and worked my way through the http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest by Rysc and that helped a lot I think. I created a 1 bit test project with a 1 bit address, data in, data out & clock to explore the timing and delays.

Since my data writes (FPGA->CPU falling edge latch) depend on the address read (CPU->FPGA rising edge latch) I thought this was similar to the DDR examples so I duplicated my min&max for rising and falling edges then set a false path between falling & falling.

Transfers only occur to the falling edge so is this the correct approach or is there a better method?

Do the min & max values for the non-transfer edges actually matter, I copied the correct edge values but should I set these to zero or something highly permissive? (If I leave these timings out I get warnings from timequest)

create_generated_clock seems to happily create virtual clocks in Quartus Prime Lite 17.1. The clocks look OK in the TQ clock tree but Google found me some posts wrt Quartus II saying create_generated_clock does not do what you expect/work.

Is create_generated_clock OK to use to make a virtual clock in QP 17.1?

My system runs stably with the following SDC constraint file:

# needed?
set_time_format -unit ns -decimal_places 3
#  physical clocks
create_clock -name clk_2MHzE -period 500 
create_clock -name clk_8M_in -period 125 
#  create on FPGA FLASH clock
create_generated_clock -name clk_flash -source  -divide_by 16 
#  parasite clock at the pin
create_generated_clock -name parasite_phi0_out -source }] 
#  create external parasite cpu clock 3ns rise & 6ns fall delay
# create_generated_clock -name parasite_phi0_ext -source  -offset 4.5 
create_generated_clock -name parasite_phi0_ext -source  -edges {1 2 3} -edge_shift {3 6 3} 
#  create clock at host CPU
# create_clock -name host_2MHzE_ext -period 500
create_generated_clock -name host_2MHzE_ext -source  -offset -10
#  name pll clocks
create_generated_clock -name parasite_phi0 -source }]
# create_generated_clock -name parasite_phi0_x3 -source }]
#  pll
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
#  clock groups
set_clock_groups -asynchronous 
	-group  
	-group  
	-group  
	-group  
		cg|internal_pll_inst|altpll_component|auto_generated|pll1|clk 
		parasite_phi0 parasite_phi0_out parasite_phi0_ext 
		}]
# 
#  host i/o
#  HOST->FPGA addr
#  setup: 140ns after falling edge (R6502)
#  hold: 15ns after falling edge (65C02)
#  buffer delay: 3ns - 5ns
#  max = 140+5, min = 15+3
set_input_delay -clock { host_2MHzE_ext } -clock_fall -max 145  host_r_nw host_tube_n}]
set_input_delay -clock { host_2MHzE_ext } -clock_fall -min 18  host_r_nw host_tube_n}]
#  HOST->FPGA data
#  setup: 110ns after rising edge (65C02)
#  hold: 30ns after falling edge (65C02)
#  buffer delay: 3ns-5ns
#  max = 110+5, min = 30+3
set_input_delay -clock { host_2MHzE_ext } -clock_fall -max 110 }]
set_input_delay -clock { host_2MHzE_ext } -clock_fall -min 33 }]
set_input_delay -clock { host_2MHzE_ext } -add_delay -max 110 }]
set_input_delay -clock { host_2MHzE_ext } -add_delay -min 33 }]
set_false_path -from  -to 
#  FPGA->HOST data
#  setup: 60ns before falling edge (65C02)
#  hold: 10ns after falling edge (65C02)
#  buffer delay: 3ns-5ns
#  max = 60+5, min = -10+3
set_output_delay -clock { host_2MHzE_ext } -clock_fall -max 65 }]
set_output_delay -clock { host_2MHzE_ext } -clock_fall -min -7 }]
# #
# # parasite i/o
#  PARA->FPGA addr
#  setup: 9ns after falling edge (R6502)
#  hold: 7ns after falling edge (65C02)
#  buffer delay: 3ns-4ns
#  max = 9+4, min = 7+3
set_input_delay -clock { parasite_phi0_ext } -clock_fall -max 13  parasite_r_nw}]
set_input_delay -clock { parasite_phi0_ext } -clock_fall -min 10  parasite_r_nw}]
#  PARA->FPGA data
#  setup: 8ns after rising edge (measured)
#  hold: 6ns after falling edge (measured)
#  buffer delay: 3ns-5ns
#  max = 8+5, min = -6+3
set_input_delay -clock { parasite_phi0_ext } -clock_fall -max 13 }]
set_input_delay -clock { parasite_phi0_ext } -clock_fall -min -3 }]
set_input_delay -clock { parasite_phi0_ext } -add_delay -max 13 }]
set_input_delay -clock { parasite_phi0_ext } -add_delay -min -3 }]
set_false_path -fall_from }] -fall_to 
#  FPGA->PARA data
#  setup: 10ns before falling edge (guess)
#  hold: 10ns after falling edge (guess)
#  buffer delay: 3ns-5ns
#  max = 10+5, min = -10+3
set_output_delay -clock { parasite_phi0_ext } -clock_fall -max 15 }]
set_output_delay -clock { parasite_phi0_ext } -clock_fall -min -7 }] 
# 
#  SRAM i/o
#  FPGA->SRAM addr :
set_output_delay -clock { parasite_phi0 } -clock_fall -max 10 }]
set_output_delay -clock { parasite_phi0 } -clock_fall -min 0 }]
#  FPGA->SRAM wren :
set_output_delay -clock { parasite_phi0 } -clock_fall -max 10 
set_output_delay -clock { parasite_phi0 } -clock_fall -min 0 

Since I want to reconfigure the PLL at runtime and I have the clocks being derived from the megafunction settings in the timing analysis, how do I define an alternate clock (say 3MHz) for the PLL outputs [1] & [2]? Do I also need to define a full set of alternate phi0 clocks?

Thanks

Chris