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Altera_Forum
Honored Contributor
7 years agoHi Anand
Thank you for your quick response. --- Quote Start --- To see huge diffrence in temperature reading, run board for longer time by utilizing most of the FPGA resourceor or by using test setup like ESS or simply using blower. --- Quote End --- The temperature reported responds to freezer spray so I am happy that the result is not stuck - it's just way off. The offset seems to be pretty consistent for each board too; the same firmware in different boards yields different offsets but power-cycling/modifying firmware, eg, changing IP core configurations and rebuilding, on a single development board gives repeatable results. --- Quote Start --- It is based on your design kindly check example 3 & 4 in below link. https://www.altera.com/en_us/pdfs/literature/dp/max-10/pcg-01018.pdf --- Quote End --- I believe I have followed the guidelines and our design conforms with example 3. Supplies are shared where possible (with the suggested filters where appropriate) and we are using linear regulators rather than switchers. The supply voltages are as follows:- VCC = 1.2V
- VCCA = 2.5V
- VCCINT = 1.2V (via dedicated ferrite bead + extra decoupling)
- VCCD_PLL1 and VCCD_PLL2 = 1.2V (via dedicated ferrite bead + extra decoupling)
- VCCA_ADC = 2.5V (via dedicated ferrite bead + extra decoupling)
- VCCIOA = 2.5V (via dedicated ferrite bead + extra decoupling)
- VCCIOB and VCCIO2 = 2.5V
- VCCIO3, VCCIO4, VCCIO5, VCCIO6, VCCIO7 and VCCIO8 = 3.3V