MAX V: Using an input clock signal for logic, and sending it back out for clocking

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I am, however, unable to have this clock signal appear externally on an output pin.

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What have you tried? An input can be routed to an output using a single line of code, eg., VHDL

clkout <= clkin;

So long as you have pin assignments for clkin and clkout, this should work.

However, Quartus will likely warn that clkout is not derived from a dedicated PLL clock output and is likely to have excess jitter (at least it does on the FPGA devices). Depending on your application, you can choose to ignore that.

Cheers,

Dave