Honored Contributor
Honored ContributorThis has been solved for a while now, but, I thought I'd post an update on this issue in case it would help anyone out.
Upon further investigation, the issue was related to an impedance mismatch on the JTAG lines, TCK specifically. The USB blaster is designed with very fast rise times using low impedance 25ohm transmission lines. My board was designed with a 50ohm controlled impedance which caused a mismatch and related reflections at the JTAG connector. The positioning of the Stratix device and routing of the TCK line were such that the reflections caused a slight flattening of the TCK line right at the threshold which was causing "false" clock edges to be detected by the Stratix. On the scope, the signals looked quite clean and only a very slight flattening could be observed (no ringing), however, it also worked reliably with the scope probe (10Mohm / 3.9pF) attached. I suspect, without the probe the flattening/ripple may have been more pronounced and enough to overcome the specified hysteresis. Also, had the TCK trace length been slightly longer or shorter the flattening would have been moved away from the threshold crossing and there would have been no issue. In the end, a 56pF capacitor was added to the TCK line which slowed the edge down enough so it wasn't an issue.
New ContributorHi, where did you find that the USB blaster has line impedance of 25 Ohms, I don't see line impedance in the Intel FPGA USB Download Cable User Guide.
I am also having a JTAG detection issue on some of my boards, and I see that my TCK signal has a voltage drop from VDD which would be consistent with mismatch between 50Ohm on PCB and 25 Ohm line in blaster. However, I don't see any voltage drop on the other JTAG signals and all my lines are the same impedance. Where did you see that the line impedance is 25 Ohms?
