Honored Contributor
Honored ContributorI was reading the power integrity (http://www.altera.com/support/devices/power/integrity/pow-integrity.html) article on Altera's website and came across the recommendation for the Bulk Capacitor (47uF to 100uF). I'm supposed to have one 47uF-100uF capacitor for every two VCCIO banks. The chip I'm using only has two banks, so that means just one 47uF capacitor.
My question now is, how to feed power to the decoupling capacitors? As of now, the power is fed directly from the source via a star-network. Each VCCIO/VCCINT pin is connected on its own via a 20mil trace. If I include the bulk cap, should I feed the power to the decoupling capacitors FROM the 47uF cap? In other words, make a localized star network for the chip rather then connecting them to the board network for power? This is what the schematic on the website seems to suggest. I obviously don't have a Vcc plane (or an unbroken ground plane).
