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Altera_Forum
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14 years ago

Max V Hardware Implementation

This is the first time I'm implementing a CPLD and so I came here looking for some advice. The following schematics show how I've wired the JTAG connector and also the bypass caps. I intend to run al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks guys. I was going over the section "Power Up Sequencing" in the Max V Handbook. While I know that the Max V supports any power-up sequence, the following caught my eye:

--- Quote Start ---

When VCCIO and VCCINT are supplied from different power sources to a MAX V device, a delay between VCCIO and VCCINT may occur. Normal operation does not occur until both power supplies are in their recommended operating range. When VCCINT is powered-up, the IEEE Std. 1149.1 JTAG circuitry is active. If TMS and TCK are connected to VCCIO and VCCIO is not powered-up, the JTAG signals are left floating.

Thus, any transition on TCK can cause the state machine to transition to an unknown JTAG state, leading to incorrect operation when VCCIO is finally powered-up. To disable the JTAG state during the power-up sequence, pull TCK low to ensure that an inadvertent rising edge does not occur on TCK

--- Quote End ---

The last paragraph concerns me. I do have a pull down resistor (1K) on TCK. Does the paragraph imply that I should pull this line low ONLY during power-up or should is it implying that a pull down resistor is all thats needed to avoid this unknown JTAG state issue.