Max V Extending JTAG?

By definition, the Altera IP blocks cannot do anything unless the physical capability (in this case, a connection from the non-programmable JTAG logic to the programmable logic blocks) is present on the chip. So the Altera JTAG extension IP megafunction (with its copious collection of additional features) obviously works by somehow instructing the logic compiler and assembler to connect the logic blocks programmed with the IP megafunction to the on-chip fixed JTAG logic blocks.

So the question was how to access that connection ability myself, pairing it with much leaner logic suited to the application.

As for the missing listing in Quartus, I realize now that some obscure document mentioned this might be disabled when the telemetry/feedback component was turned off, which is standard practice when developing my own IP.

As for my requirements, the alternative would simply be to not integrate the two functions and either use additional pins on board-to-board connections to carry both JTAG and private data lines, OR to use a bed-of-nails to do one-time programming of the CPLD and hope there is never a need to field upgrade that part of the design, in which case I can also use a less powerful Max3032 in a 0.5mm TQFP-44 rather than the more expensive to accommodate 0.4mm EQFP-64 package and extra LDO used by Max V.