Max V Extending JTAG?

I think you need to reconsider your 'requirements'. Yes, the JTAG to Avalon Master Bridge IP is going to be a little large - it'll consume over half of the resources in largest MAX V device. However, without it you won't have an "actual interface between the on chip jtag tap circuits and the logic blocks..."

The JTAG interface allows you to program the non-volatile memory from which the device configures itself. At power up the device configures from this non-volatile memory. There is no default interface between the JTAG and the logic. This interface will only exist if your design implements it. I'd suggest the only practical way to do this is with Altera's JTAG IP. I'm not even sure if there is another way of doing it.

Hence, my suggestion that you reconsider your requirements. Either an alternative interface into your MAX V logic or a larger device, probably from another family (large MAX V's are relatively expensive), that will support the necessary Altera IP.

The JTAG to Avalon Master Bridge IP should exist in the web edition of Quartus. Type 'JTAG' in under the IP Catalog.

Cheers,

Alex