max number of bit of a multiplier in statix III

Rather than guessing, why don't review the detailed DSP blocks chapter in the Stratix III Device Handbook. It clearly tells about 36 x 36 "native" (hardwired) multiplier support and larger constructs like 54 x 54. In so far, there's surely no restriction imposed by the Stratix FPGAs. Maximum speed will of course depend on the implemented multiplier width. You'll find some basic performance numbers in the Device Handbook as well.