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Altera_Forum
Honored Contributor
Honored Contributormax number of bit of a multiplier in statix III
Hi, I am implementing a DSP algorithm on Stratix III device. Internally, I am using 16 bit and this bit width does not give a right calculation. I increased upto 32 bit but still same. ...
Altera_ForumHonored Contributor
Honored ContributorRather than guessing, why don't review the detailed DSP blocks chapter in the Stratix III Device Handbook. It clearly tells about 36 x 36 "native" (hardwired) multiplier support and larger constructs like 54 x 54. In so far, there's surely no restriction imposed by the Stratix FPGAs. Maximum speed will of course depend on the implemented multiplier width. You'll find some basic performance numbers in the Device Handbook as well.
The reported problems of getting incorrect results with 32 bit DSP sounds rather like a design fault. Did you check the data flow by pencil and paper?
