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Does the I2C master keep an I2C speed of 100 kHz and the other related timing requirements? The UFM-I2C interface is designed as synchronous logic clocked by the MAX II internal oscillator, which isn't very fast, it may have problems if the I2C interface is operated beyond the basic specification. I didn't yet use the I2C interface and am not aware of possible bugs. But the complete interface logic is present as HDL text in the I2C component file, you can review it and check it's operation in a simulation.
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FvM, Thanks for your advices very much!
I had configured the master's I2C speed as 100kHz firstly, but the result was the same as above. Then I configured some other frequencies, such as 80kHz, 50kHz, but the I2C megafuction couldn't work normally as well, that's its acknowledges couldn't be detected most of the time. I don't find the DSP master have any other configurations for the I2C module's other timing requirements. Did the problem have relationship with the version of Quatus II? I used the Quatus II 8.0.
Did anyone encounter the same problem with me? Please give your advices. Thanks!
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