MAX II Decoupling Capacitors

The design rule I basically use is the largest available capacitance in the least inductive package per pin.

So for most TQFP devices I use an 0603 size device typically about 1uF per pin using a low inductance PCB footprint.
This means VIA in PAD, if possible, or else two VIAs per pad with PCB surface stubs that are as short as possible.

For BGA devices I like to go with VIA in PAD and bridge an 0402 device across a power/ground pin pair under the device.
Usually on the 45deg diagonal works best for fine pitch BGA device footprints.

Larger bulk capacitors in the 10uF-47uF range can surround the device, but they are nowhere near as critical.

Anybody that says spray a range of small devices in the 100pF to 10nF range are spouting nonsense IMHO.

Done this for 25+ years of high end design using ASICs, FPGAs, CPUs and other state of the art devices.
Never served me wrong.