Max II Config Complete Detection

To reset all registers to a defined state, you don't need a reset controller however. Simply assigne initial states to the signals. They are converted to power on set/resets. You should consider however two points:

MAXII (as well as many newer FPGA families) has only asynchronous reset, not set.

- This means, the compiler inverts the register polarity internally to achieve an asynchronous set.

- You can't use both, asynchronous set and reset for a register

In some cases, you may want to assure the reset to be synchronously released. Then you need a kind of reset controller. Without an external reset input, I mostly use a reset counter, that should even resist an uncleanly starting clock. In VHDL, it looks like below:

signal start	: INTEGER range 0 to 7 := 0;
...
IF rising_edge(clk) THEN
  IF start < 7  THEN
    start <= start + 1;	
    reset <= '1';
  ELSE
    Reset <= '0';
  END IF;