Max 4x recovery clock implemented on Cyclone 3

from datasheet, the IO / Core clock seems to be 300MHz - 400MHz max but I don't think we can implement a 100MHz serial LVDS with 4x clock recovery in a cyclone.

want to know if anyone has done it? i mean how do we know the max frequency we can recover serially from device datasheet?

i also understand there could be many methods of bit sampling (for e.g. quad-phase bit sampling without having to 4x the input bit frequency)