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check ALL pins between the pdf and your schematics & layout
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VCCINT and VCCIO are connected to 3.3 V; GNDINT and GNDIO are connected to 0 V; TDI, TCK, TMS and TDO are connected to pull-down resistors and to the Altera Byte Blaster; GCLK and DEV_OE and DEV_CLRn pins are used as "User I/O".
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also use Quartus -> Assignments -> Pin Planer and check all entries.
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All "User I/O" outputs pins have a high impedance load; all "User I/O" input pins have an input between 0 V and 3.3 V. All unused "User I/O" pins have either an input between 0 V and 3.3 V or are unconnected.
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check your project settings for this device how it should handle unused pins.
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They are reserved "as input tri-stated".
On the conditions above, can any cause of the device destruction be excluded except the following?
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ESD problems in your enviroment [...] voltage over and undershots on input pins, gnd bouncing
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