--- Quote Start ---
It fixed it because you changed the design, signals got re-routed and the problem went away. The compiled design will be different from one compile to the next even with the most minor of changes.
--- Quote End ---
Yes, obviously. No doubt about that! I was just wondering if anyone had an idea as to *why*.
Maybe if I rephrase: Physically, inside the FPGA, you have internal connections between the LUTs. When I decide to feed one of those signals to a pin, I assume it must run through a buffer that was not there before. What is it about the buffer (or other aspects of this connection) that would change the circuit so dramatically? The ideal buffer has no effect on the input circuit-- and the whole reason I was feeding this signal to a pin was to see what it was doing, not to fix a problem.
Does it have to do with a pull-up or pull-down changing a 1 to a 0, or vice-versa, for example? I tried to change this internally to test it, but it did not help. But maybe I did it wrong.
Basically, something seemed to change when it should not have. I suspect it is a bug in the Quartus compiler, but I have been wrong on that sort of thing many times before! :)
Thanks for your help!
Honored Contributor
