Honored Contributor
Honored ContributorI am having a similar problem:
My Max10 design was having bizarre timing issues. It worked fine on an eval board, but in my produced design, the timing was really weird- seemingly random. I am programming this schematically. In an effort to diagnose the problem, I ran one signal out to a pin connected to a FET (which controls an LED). Once I did that, the signal I was trying to look at worked AND the whole FPGA timing problem disappeared! It seems I can completely fix the problem by feeding this one internal signal out to a pin (even an unused pin with no FET). Once I remove the pin assignment, the problem reappears. So, even though it now works, I would like to know *why* this fixed it before we go to production. Any clues? Sorta seems like it needs a pull-up, pull-down, or buffer(?). Thanks!
