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tulip007
New Contributor
New ContributorMAX 10 Tcout value
What is the spec for the Tcout value referenced in table 61 of the MAX 10 FPGA Device Datasheet? It defines it as the delay from clock pad to I/O output register but does not list specific values per...
ShengN_altera
Super Contributor
Super ContributorHi,
Clock pad to output register delay is the time it takes for a clock signal to travel from the point (at the clock pad) to the point where it triggers an action in a flip-flop or register (at the output register).
