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IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
4 years ago
Solved

MAX 10 single supply LVDS max data rate

Hi all! I work with Intel MAX 10 FPGA, single supply (10M16SAU169I7G) The aim is to implement ADC interface using LVDS - desired speed up to 400 Mbps. I created test project with soft-LVDS an...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    4 years ago

    The Quartus does not consider the electrical and switching characteristics. For an IO the limit is put up by the IO standard, structure of the IO and the technology used.

    Please consider the datasheet value as max data rate.


    Regards


Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

The timing report showed the highest achievable frequency of the internal logic and not the physical limitation of the IO pin. On hardware, the frequency will be limited by the numbers mentioned in the datasheet.


Regards


  • IDeyn's avatar
    IDeyn
    Icon for Contributor rankContributor
    4 years ago

    Hi, Ash_R_Intel.

    Thank you very much for your answer.

    Well, if so, then it's strange, I suppose, because we need to check in this case for all external interfaces whether our timings exceed the values in the datasheet . I always thought that TQ uses timing data also for the I/O buffer. So what in this case limits the speed?

    --

    Best regards,

    Ivan