MAX 10 Sample & Hold Timing

I have read all of that documentation before. The block diagram early in that file that shows the "ADC Hard IP Block" shows a sample/hold amplifier before the A/D converter, but nowhere have I been able to find any documentation of how the S/H function is controlled and when it switches from "sample" mode to "hold" mode for the A/D converter. I need to convert a signal with limited valid level timing (500kHz sample rate) so I need to understand the timing of the S/H function so I can control the phasing between the S/H and the analog input. The S/H must switch from "sample" to "hold" during the valid level time on the analog input so the A/D has a stable input signal to convert. It's not a matter of what clock frequency I'm using. I need to know more about the timing of the S/H function with respect to the A/D control signals.