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Altera_Forum
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9 years ago

Max 10 IO status when Jtag Programming

Hi there, I use Max 10 10M04DAU324 Series FPGA in our design. Only I konw that IO status keeps tri-state with internal weak pull-high when CFM to SRAM(config mode) as attachment picture sh...
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Altera_Forum
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9 years ago

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In a normal ISP operation, to update the internal flash with a new design image, the device exits from user mode and all I/O pins remain tri-stated.

--- Quote End ---

Whenever the device is not in user mode all I/O are tri-stated. This includes when the device is being configure via JTAG.

See the 'max 10 fpga configuration user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_config.pdf)'.

Cheers,

Alex