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But since you mentioned I/O voltages, I see on the MAX 10 datasheet that the recommended VCCIO voltage for all banks should be 3.135V...3.465V for a 3.3V core voltage.
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That's not how I read the datasheet - I think it means that if you have selected 3V3CMOS as the I/O standard for those pins, then VCCIO must be in that range; similarly for all the other standards.
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I originally imagined that if I set VCCIO2 to, lets say, 2V, and VCCIO3 to 2.5V, all I/O's on bank 2 will output 0V for logic state 0 and 2V for logic state 1, and the I/O's on bank 3 will output 0V and 2.5V. But confirming: this is not true, right?
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The behaviour isn't defined for random voltages (though it would probably work), only where you pick an I/O standard in the compiler and then supply the matching voltage on VCCIO.
But you should be able to use multiple I/O voltages even on a single supply part (though personally I've only done so on the dual supply parts - IMO, the main use of the single supply parts is when the whole system is 3V3).
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Actually, I originally imagined that I could set a VCCIO to even 5V, and it'd go 0V and 5V. It'd be nice, but, oh well...
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5V is well outside permitted range and will probably destroy the part...
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Also, currently I'm using external drivers/buffers ICs to drive some 3.3V signals out of the FPGA because those signals go outside the board, thru a cable, into another board. And I don't want to put this load on the FPGA. Is this a waste of resources? Can the FPGA outputs indeed drive those signals strongly enough to overcome the impedances/capacitances of the path to the next board? The cable isn't that long. It can be from 10cm to 50cm, and it ends on drivers/buffers inputs.
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Outputs are quite strong; more of a concern in that sort of setup is meeting the overshoot requirements on any inputs that you also intend to connect to a long cable.
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