--- Quote Start ---
Beware that that only applies to the "single supply" versions of the MAX10 - "S" in the partnumber after the size - which in turn are only available in certain package options.
So for your job you could use the 10M02SCE144C8G (144 QFP package), but not the 10M02DCV36C8G (36-pin tiny package, but only available in "dual supply").
Note also that the MAX10 "dual" supply is "dual" in the same way as Cyclone 3/4 are "dual" supply - actually 3 different voltages needed unless your I/O voltage happens to be the same as one of the internal voltages.
--- Quote End ---
Ah thanks. Yes, the chip I'm using is the 10M02SCE144C8G. I did originally intend to go with the 10M02DCV36C8G, since it's cheaper and will do what I need. But the BGA pitch did scare me... /blush
But since you mentioned I/O voltages, I see on the MAX 10 datasheet that the recommended VCCIO voltage for all banks should be 3.135V...3.465V for a 3.3V core voltage. I originally imagined that if I set VCCIO2 to, lets say, 2V, and VCCIO3 to 2.5V, all I/O's on bank 2 will output 0V for logic state 0 and 2V for logic state 1, and the I/O's on bank 3 will output 0V and 2.5V. But confirming: this is not true, right? Actually, I originally imagined that I could set a VCCIO to even 5V, and it'd go 0V and 5V. It'd be nice, but, oh well...
Also, currently I'm using external drivers/buffers ICs to drive some 3.3V signals out of the FPGA because those signals go outside the board, thru a cable, into another board. And I don't want to put this load on the FPGA. Is this a waste of resources? Can the FPGA outputs indeed drive those signals strongly enough to overcome the impedances/capacitances of the path to the next board? The cable isn't that long. It can be from 10cm to 50cm, and it ends on drivers/buffers inputs.
Honored Contributor
