Altera_ForumHonored Contributor8 years agoMAX 10 in place of Cyclone IV Well, this seems fine to me, but I thought I'd ask the experts before doing it: I've made a VHDL design that's currently working on a Cyclone IV E. It uses the internal RAM (dual port mode), ab...Show More
Altera_ForumHonored Contributor8 years agoMAX10 is also my first choice for small designs like the mentioned one.
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information