--- Quote Start ---
You could create a Platform Designer (aka Qsys) system design and use the tri-state components (generic tri-state controller, tri-state conduit bridge) to do this instead of creating your own logic.
--- Quote End ---
Hi SStrel, in first thank for prompt answer, I am far from LAB to apply a test now.
Here attached the code I wrote and TCL script for QSYS. Compared to UNIVERSITY program (seen later on seeking your suggestion), seems very close, U.P. is written in Verilog I prefer VHDL.
On "Generic Tristate Controller" you suggested there is a device close to mine, IDT71V416, using this block device is forever 32 bit.
If I select that device then edit all parameters adapting to device, it appear as tristate driver more than an SRAM controller. I suppose some other block need be attached and it is not clear to me now how to use these blocks.
Doing this, portability across family and vendors broke and here is why I prefer wrote my code.
I'm also stuck at quartus version 15.1, new version report error if pin near clock get used and offer no way to override compiling a previous working design.
Best regards
Roberto
Honored Contributor
