Max 10 ADC Simulation - Can't get it to work properly

Thanks irish but that vid doesn't mention simulation at all.

I've now got real hardware and can confirm that the simulation doesn't drive the response signals at all though I am setting the ADC up correctly.

To get around my simulation issue I wrote the following. Maybe it is of use to somebody. It is in noway functionally complete.

module ADCModel (
	input clock_clk,
	input reset_sink_reset_n,
	input adc_pll_clock_clk,
	input adc_pll_locked_export,
	input sequencer_csr_address,
	input sequencer_csr_write,
	input  sequencer_csr_writedata,
	input sequencer_csr_read,
	output reg  sequencer_csr_readdata = 32'd0,
	output reg response_valid = 1'd0,
	output reg  response_channel = 5'd0,
	output reg  response_data = 12'd0,
	output reg response_startofpacket = 1'b0,
	output reg response_endofpacket = 1'b0
);
	wire go = reset_sink_reset_n && adc_pll_locked_export && sequencer_csr_readdata;
	
	always @ (posedge clock_clk) begin
		if (sequencer_csr_write && !sequencer_csr_address) begin
			sequencer_csr_readdata <= sequencer_csr_writedata;
		end
	end
	localparam NUMBER_OF_CHANNELS = 5'd4;
	
	reg  adc_clk_store = 2'd0;
	wire  response_channel_next = (response_channel >= NUMBER_OF_CHANNELS - 5'd1) ? 5'd0 : response_channel + 5'd1;
	always @ (posedge clock_clk) begin
		adc_clk_store <= {adc_clk_store, adc_pll_clock_clk};
		if (go) begin
			if (adc_clk_store == 2'b10) begin
				response_valid <= 1'b1;
				response_channel <= response_channel_next;
				response_startofpacket <= (response_channel_next == 5'd0);
				response_endofpacket <= (response_channel_next == NUMBER_OF_CHANNELS - 5'd1);
				case(response_channel_next)
				5'd0:		response_data <= 12'h111;
				5'd1:		response_data <= 12'h222;
				5'd2:		response_data <= 12'h333;
				5'd3:		response_data <= 12'h444;
				endcase
			end else begin
				response_valid <= 1'b0;
				response_channel <= 5'd0;
				response_data <= 12'd0;
				response_startofpacket <= 1'd0;
				response_endofpacket <= 1'd0;
			end
		end else begin
			response_valid <= 1'b0;
			response_channel <= 5'd0;
			response_data <= 12'd0;
			response_startofpacket <= 1'b0;
			response_endofpacket <= 1'b0;
		end
		
	end
	
	
endmodule