Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi siliconvalley,
The FPGA normally pulls the nSTATUS pin low when an error occurs during configuration. 1.Check the pin nConfig and nStatus in reset state it should be high state. 2.Kindly recheck check the drive strength of the source. Is Source giving 3.3 volts, 3A & voltage across all pin(3.3) is drooping or only the nSTATUS pin. 3.Is .pof generated with correct configuration. 4.Is there any configuration in board available to select the different sectors of the flash to load different program? 5.Try to load .jic using flash loader instead of .pof. or erase the EEPROM and try it again. Can attach schematic/screenshot of schematic. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)