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Altera_Forum's avatar
Altera_Forum
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9 years ago

Marvell 88EE1111 PHY tranciever MDIO reg configuration

I'm trying to troubleshoot PHY for my dual Ethernet design on the DE2-115 Cyclone IV board. (I have to load my *.elf file twice for some reason for my design to work). In trying to figure ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Thanks, this helps a lot. We are going to try to set it up for MII and then proceed to RGMII. We are curious as to what register values are written to the phy registers. Would you be able to send that to me?

With RGMII, the Tx and Rx clocks run at double data rate and are skewed in a specific way to process the data correctly. We are unable to see what the data looks like coming out of the Ethernet port. That is our main issue.