Marvell 88EE1111 PHY tranciever MDIO reg configuration

FPGA,

To remove line loopback and ensure both TX and RX delays for the DDIO clock are set, be sure to set the 88EE1111 register 20 to 0x0082. Bit 14 controls line loopback. Bits 15 and 1 are RX/TX delay.

I do have PLL and DDIO modules instantiated at the toplevel, apart from my Nios II system. The best way to describe it would be to reference the excelent tutorial for the TSE on the DE2-115 (can be found at https://www.altera.com/support/training/university/materials-tutorials.html). Page 21 has a typo (Ethernet port 2 does not exist. It should read "Ethernet port 1"). It includes commands needed to set up auto-negotiation and the GMII transmit speed as well.

I hope that works!

For further development, I would definitely recommend the UDP Offload Example at AlteraWiki!