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agaripcan6223
New Contributor
New ContributorManual fitting with chipplanner
Hi, I want to generate metastability-based true random numbers using a model where 256 R - S latches are connected in parallel, as in Figure 1. For this, I have to place the NAND gates that make up e...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
You can prevent optimization by setting the preserve synthesis attribute on the register. You may refer to the syntax below.
Verilog: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_file_dir_preserve.htm
VHDL: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_file_dir_preserve.htm
Thanks.
Best regards,
KhaiY
