Managing multiple clock domains in verilog

Cutting paths between the unrelated clock domains should do the trick. Here are a few things to check.

1 - You are using the Classic Timing Analyzer right? The Cut paths setting won't do any good if not.

2 - If the multiple clock domains are being driven from the same PLL, the timing analyzer may determine them to be related (because they are). Are you driving your different clocks from the same PLL?

3 - You may wish to consider using TimeQuest. The learning curve will cost you several days but it does give you more control over these things.

Jake