Making smart FIFO ?!

My FPGA is Stratix II GX 90 with more than 5 millions of bits of memory but I think I will make a circular buffer because I don't need to have all the image datas at the same time. I can have just one piece, make image processing on this piece, then go processing the next piece and so on.

Actually, just like you said, I want to align my first useful data bit receive to 0 in my FIFO and then put all other datas after that, except last data bits from every end of line.

Thank you for all. Nice holliday!

If someone else can help me, it will be appreciate.

Fabrice.