Honored Contributori have three nos value like a , b and c. and each are 1 bit binary value. how i convert it into a three bit binary value where a is the most significant bit and c is the least significant bit and b is the middle bit. example: if a=1 , b=0 and c=1 then how i make it a three bit binary valu which containing as x[2..0] or x= value of [a b c]
Honored ContributorThat's called concatenation......
reg [2:0] x; assign x = {a,b,c};Honored ContributorYou might want to have a look at this:
http://www.asic-world.com/verilog/verilog_one_day.html I found it very useful way back when I was staring out with Verilog.Honored Contributori work with fpga in block diagram environment not in hdl language.. so please u may suggest me the concatenation technique in block diagrame environment....
Honored ContributorYou can name a wire something like x[2:0]
Then the ones you want individually can then be named: x[0] x[1] x[2] And it should concatenate and associate them together at compile time. NOTE: You should NOT connect the wires together.
