Making a counter from 50MHz Clock?

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You have it in NCOs hidden there.

just use a suitable width adder starting from zero adding 3579545 every system clock and carrying over result after (50 million -1) i.e. if it becomes > (50 million-1) then subtract 50 million from it and keep going nonstop.

Then MSB is your rate.

The generated clock is correct rate-wise but duty cycle varies.

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so then:

if ((counter > 49,999,999) AND (counter < 3579545Hz))
    counter = counter - 50,000,000
endif;
if(counter == 3579545Hz)
    clk_enable <= "1"
else 
    clk_enable <= "0"
endif;

is that what i need to do? (not actual VHDL syntax :) )