Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Making a counter from 50MHz Clock?

Hi, I know this might be a really silly question but I can't seem to get the theory down into HDL: I want to make a 3579545Hz clock from a 50MHz clock input: i know that --- Quote Start...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

You have it in NCOs hidden there.

just use a suitable width adder starting from zero adding 3579545 every system clock and carrying over result after (50 million -1) i.e. if it becomes > (50 million-1) then subtract 50 million from it and keep going nonstop.

Then MSB is your rate.

The generated clock is correct rate-wise but duty cycle varies.

--- Quote End ---

so then: 


if ((counter > 49,999,999) AND (counter < 3579545Hz))
    counter = counter - 50,000,000
endif;
if(counter == 3579545Hz)
    clk_enable <= "1"
else 
    clk_enable <= "0"
endif;

is that what i need to do? (not actual VHDL syntax :) )