When i look at "Table 34. High-Speed I/O Specifications for Cyclone V Devices" in Cyclone V Device Datasheet at page 47
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf
The highest clock input frequency for true differential standards is 437.5 which in best case can support data rate up to 875 Mb/Sec in DDR while i'm looking for almost twice that rate.
I see that Arria 10 support up to 1,600 Mb/Sec in DDR mode but these FPGA devices are relatively expensive....