LVDS Pinning Issue for Arria 10 GX Development Kit with FMC Loopback Card

Hello,

I have Arria 10 GX Development Kit which includes FMC loopback card in the box. My goal is testing LVDS SERDES Intel FPGA IP using loopback mechanism. I generated separate LVDS Tx and LVDS Rx IPs with the following configurations.

Data rate: 600 MBps
SERDES factor: 8
# of channels: 2
External PLL is used for both IPS.

Analysis & Synthesis part of compilation was done successfully. However, I have trouble to find proper pins for TxClock and RxClock pairs.

For LVDS Tx IP I used ref clock of PLL which is located in IO Bank 3A (BD24-BC24). This is the only available reference clock on board for IO banks 3A, 3B and 3C.

Since I plan to use FMC loopback card, all possible LVDS data and clock pairs (for Rx and Tx) are located in IO Bank 3B and 3C.

Place & Route fails to find proper pins with the current pinning constraints. As far as I understood from device handbook of Arria 10, reference clock and LVDS pins should be located in the same IO bank. Unfortunately, I could not find such pins with the eval kit and FMC loopback card.

Is there an example design which shows proper pinning for this case? I also appreciate if anyone has suggestions for pinning.

Note: By ignoring FMC loopback card, I used only IO bank 3A for pin assignment. This time Place & Route compilation was completed without an error.

Thanks in advance.