Altera_Forum
Honored Contributor
17 years agoLVDS I/O termination
Is an external 100Ohm resistor required at the input of an LVDS receiver I/O pair for the Cyclone III devices? The literature seems to suggest yes and no. Also, if I have "rx_in" as a single-channel LVDS serial input to my deserializer on the FPGA, is it correct to assume that "rx_in", and its complement "rx_in(n)" which the fitter autmoatically assigns, will be converted into a single serial bitstream by the LVDS I/O pair and presented to my deserializer as one rx_in?