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the key is the pulse width is very narrow, and some pulses can not trigger counter.
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Did you perform a timing analysis and determine the minimum acceptable pulse width using TimeQuest?
Since your current design uses a counter directly, you do not give the synthesis tool much in the way of options for placing logic. If you use the scheme I suggest, then you can use an IOE register on the input signal. Since these registers work with DDR LVDS signals up to close to 1Gbps, and SERDES LVDS up to 1.6Gbps, there is a good chance you can get it to work.
Cheers,
Dave
Honored Contributor
