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I designed a counter, used to LVDS level pulse signal count. The number of pulses per second is a few hundred or so. Pulse width is random, from 1ns to 3ns, need to count the number of pulses, the interface is LVDS, I use the LVDS IO direct input pulse, with verilog write counter. Result, the counter can not count the number of pulses accurately , the count number is much less than the actual number. Is there any way to achieve LVDS High-speed counter？
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How close can two pulses be together?
I would count pulses as follows;
1) The input LVDS pulse is the clock pin on a toggle register. The output of the register will then toggle for each incoming pulse (assuming 1ns is enough of a 'clock' signal - you'll have to check the pulse high/low minimum with TimeQuest).
2) Synchronize the toggle signal to your FPGA clock domain, and generate a pulse for every change in toggle signal.
3) Count the pulses.
Cheers,
Dave
Honored Contributor
