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Altera_Forum
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15 years ago

LVDS clock outputs

Hi all, We use Stratix-IV GX (EP4SG360FF35C4) device. 1. How to specify the PLL output clock as LVDS in altpll? (This device doesn't supports "Setup PLL in LVDS mode" option). 2. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Humm okey. Would it still be better for slew rate to use the AltDDIO implemented in logic cell than feeding the pll clock directly to the LVDS IO?