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Altera_Forum
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15 years ago

LVDS clock outputs

Hi all, We use Stratix-IV GX (EP4SG360FF35C4) device. 1. How to specify the PLL output clock as LVDS in altpll? (This device doesn't supports "Setup PLL in LVDS mode" option). 2. ...
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Altera_Forum
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14 years ago

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For some reason the altDDIOs registers are not place in the IO cell, but logic cell out side it (see in the Chip Planner)

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The Cyclone II device manual clarifies:

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The DDR output logic is implemented using LEs in the LAB adjacent to the output pin.

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