LVDS clock in an SSTL bank

I have a Stratix V design where I need to bring in an LVDS clock into a bank dedicated to DDR2 (SSTL with 1.8V VCCIO). Can I run this clock directly in using LVDS levels, or does it need to be converted to SSTL levels?

The Stratix V documentation states that the dedicated input clock buffers are powered by VCCPD, which in my case is 2.5V, so this would seem to support having a clock input at LVDS levels. However I seen no info in the documentation specifically stating that I can do this.