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Altera_Forum
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17 years ago

LVDS (2.5V) in Banks where JTAG and Config Pins reside?

Hello, I want to use the Bank 2, 5 and 6 of the Cyclone II EP2C35F484 for LVDS communication. An FAE from Sasco Holz (Arrow) told me, that i should use the left and right banks for LVDS instea...
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Altera_Forum
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16 years ago

Hi Szymo,

as far as I know, you can supply the LVDS Banks VCCIO with 3,3V while choosing LVDS as I/O Standard. If you do so, you are not longer LVDS compliant, but if the Partner Device is also a Cyclone FPGA it should work properly. I used a Cyclone II as a Parallel to LVDS Interface for an LVDS Display. The Display´s National Semiconductor LVDS Chip works inside its specification even if you power the LVDS Bank with 3,3 Volt.

If you are not sure, why don´t you put the LVDS Pins into a Bank where no JTAG Pins resides in?

Sometimes it´s helpful to have a look at the Pin Connection Guidelines from Altera. For Cyclone III you can find it here:

http://www.altera.com/literature/dp/cyclone3/pcg-01003.pdf

I hope i could help you.

Stefan