LUTs vs Logic Elements/Cells

Hi,

I am currently doing initial analysis on a design. I am researching different FPGA´s regarding the required resources to implement different features.

I cannot find a method of relating the number of LUT´s used by a design and translating this into Logic Elements for the stratix range. Could you please, if possible, provide me with a good estimate for each of the stratix family?

Also if possible is it possible to use convert Logic elements from altera to logic cells in Xilinx. Are there factors that can be used between the respective families?

Basically I am looking for a general approximation of how to interchange between both LUT´s and logic elements and between logic elements and logic cells

Thank you very much for your time,

Veronica