LUT holds final value for 2x clk cycles

Dear All,

I would like to ask for your help. I have produced a LUT 11 bits wide and 12 words in length. The values are a binary representation of a sine wave.

In my process i wish to continually step through the LUT writing each value to the output "Data".

The problem i have is that in my simulation "Data" retains the last LUT value for 2 clock cycles not 1.

I assume this is because when index = words a clock cycle is consumed setting index to zero and branching back to the IF clk = 1 statement.

ENTITY clkd_rom2 IS
 GENERIC (  bits : INTEGER := 11;
    words : INTEGER := 12);
 PORT (  clk : IN STD_LOGIC;
   data : OUT STD_LOGIC_VECTOR ( bits-1 DOWNTO 0));
END clkd_rom2;
ARCHITECTURE rom OF clkd_rom2 IS
 TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits-1 DOWNTO 0);
 CONSTANT memory : vector_array := ( "01000000000",
          "01100000000",
           --more values go here.......
          "00100000000");
          
BEGIN
 PROCESS (clk)
 VARIABLE index : INTEGER:=0;
 BEGIN 
  IF clk='1' AND clk'EVENT THEN 
   IF index < words THEN
    data<=memory(index);
    index := index + 1;
   ELSE
    index := 0;
   END IF;
  END IF; 
 END PROCESS;
END rom;

Does anyone have any ideas how i can overcome this problem and loop back to the 0th index in my LUT without sacrificing a clock cycle.

I want to get the code working properly then i intend to use a much much larger ROM represenation of the sine wave possibly using a memory init. file.

Many thanks

Adrian.

PS i have .vhd and .vwf files.