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I store those as variables because every time i insert an input their values will be
changed.As far as i know variables are used inside process(because their values change every clock time) and signals are constant values.(if i am right).I will try to explain you what exactly i want to do so you can help me.
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this is incorrect.
Variables can exist in any process, function or procedure. A signal exists inside an architecture. The difference is that variables are updated immediatly, whereas signals are updated at the next delta. This can have a huge effect on the code you are writing. Take a look at the following code:
signal a, b, c : std_logic;
process(clk)
variable x, y, z : std_logic;
begin
if rising_edge(clk)
x := input;
y := x;
z := y;
output <= z;
a <= input;
b <= a;
c <= b;
output <= c;
end if;
end process;
The version using variables desicribes a 1 register delay from input to output. The version using signals describes a 4 register delay from input to output. This is because the variables are updated imediatly, they pass the value straight through. Because the signals are all updated at the same time, they are all updated at the clock edge, therefore each one is a register.
now, just to screw with your head, here is a version of the a/b/c method above, but using variables, that describes exactly the same behaviour.
process(clk)
variable a,b,c : std_logic;
begin
if rising_edge(clk)
output := c;
c := b;
b := a;
a := input;
end if;
end process;
Now, because variables before the previous one updates, this will produce a pipeline of 4 registers as well.
The trick to learning VHDL is not learning the language, but first understanding the hardware you are trying to discribe. Only then can you use tricks of the language to help you discribe things above. No offence, but it looks and sound like you are trying to write VHDL like a programming language, which it is not - it is a hardware description language.
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I want to insert some inputs(lets say 3),each of one has one weight(random).So i would like to multiply each input with its own weight and then compute the sum of them.Then i would like to compare this sum with a predetermined threshold and if the sum that i have computed is greated than this threshold its ok.But if the sum is less than the threshold i would like to correct the values of the weights so the total sum is greater than the threshold.I hope i explained it good.
P.S Sorry for my bad english
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And again, this points to you thinking VHDL is a programming language. FPGAs and hardware are very good at doing static things and doing repetative tasks. They are not good at decision making. What you want to do sounds like a very complicated task for an FPGA to do.
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