LPM_FIFO+ problem

All,

I am have a similar issue.

My setup:

Quartus 9

MAX II

Windows 10

Write clk 200ns

Read clk 200ns(shifted in phase from Write clk)

small 8bit x 8words (for testing now, will get larger when I understand what is going on)

My problem is not at the beginning but trying to read out the last word. I can write into the LPM_FIFO+. I have it set up as dual clock, but not using the DC module, (it acts the same way). My write clock is 200ns (MHz) which seems ok. I can see the address increment on my write clocks. Example: I can write 4 words without any issues, and I can read out the first 3 words, but no matter what I do, I can not read out the last word.

NOTES:

The write-empty flag goes LO upon the first write clock.. (on I expect that),

The read-empty flag goes LO around 1us after the 2nd write.????

Then the read-empty flag goes HI upon the 3rd read, the write-empty flag stays LO.

No matter how many reads I try after that, I can not read my 4th word I stored......

Also, my wr-address never decrements after each Read??? (shouldn't this count back down??) (the read address KINDA works as expected, it is delayed while writes are being made, but even though it sees the 4th read-clk, the address counts back down to 0, but no new data is available. the data that is on the OUTPUT is the 3rd word).

I do get this warning!

Warning: Assertion warning: Current device family (MAX II) does not support dual-port synchronous RAM -- implementing the synchronous RAM as a DFFE array instead

but I am assuming !! that it behaves the same way as if it was implemented using RAM.

Any ideas?

Keith