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Honored Contributor
Honored ContributorLPM_FIFO+ problem
Hi, I have used a couple of dual clock fifo's in my design and have experienced problems with reading data from them. It seems that I have to flush two null words out of the fifo's after a rese...
Altera_ForumHonored Contributor
Honored ContributorHi Kaz,
All I can say is that the rdreq that I saw on my logic analyser was not synchronous with any of my available clocks, probably because of arbitration on the PCI Local Bus. That is why I could not use a fixed clock for the rdclk signal. My 32MHz is a master clock from a crystal input to the FPGA and all other clocks down to 1MHz are created from it, so the 4MHz clock is pretty stable. I will let you know how I get on with the hardware dummy reads.
